Serial transmission of data between a processor module and peripheral elements in an electronic system is well known. The electronic system may be designed, for example, as an engine control unit, as a transmission control unit or as a brake control unit for a motor vehicle. The data transmission between the processor module and peripheral elements may be used for the triggering of the peripheral element by the processor module.
A processor module may include a computing element taking the form of, for example, a microprocessor. The peripheral elements may be formed, for example, as a monitoring circuit, particularly as a watchdog, as a serial EEPROM (electronically erasable and programmable read-only memory), as a stabilizing circuit or as an output-stage circuit, for instance, for the injection of fuel for an internal combustion engine. The processor module may also include a device for implementing the serial data transmission between the processor module and the peripheral elements. The device may be designed, for instance, as a serial interface, particularly as an SPI (serial peripheral interface)-bus interface.
For the data transmission between processor module and peripheral elements, four lines may be provided in the conventional methods and devices, namely:                a timing line for the clock-pulse transmission,        a data line from the processor module to the peripheral elements,        a data line from the peripheral elements to the processor module, and        a selection line to each individual peripheral element for controlling and addressing the peripheral element.        
The timing line may also be denoted as a clock line, and the selection line may also be denoted as a chip-select line. A device and a data-transmission method of this kind, as well as a processor module involved in the method of this kind, are disclosed, for example, in German Patent No. 100 36 637.
To reduce the radiant emittance and to improve the electromagnetic compatibility (EMC) at higher data rates, it is also conventional to transmit the timing signal and the data signal as differential signals via two lines in each instance. To that end, in each case two timing lines and two data lines are routed to the peripheral elements. The selection lines may still be provided.
This may mean that at least five lines are needed solely for the purpose of transmitting data from the processor module to one or more peripheral elements.